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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
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<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ahb_def_slave.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\BusMatrix.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can_define.vh<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can_static_macro_define.vh<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can_top.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_adder.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_ahb.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_alu_dec.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_core.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_ctl.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_ctl_add3.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_decoder.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_defs.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_dp.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_excpt.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_fetch.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_fns.vh<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_mem_ctl.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_multiplier.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_multiply_shift.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_mux4.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_ahb.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_ahb_os.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_defs.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_main.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_pri_lvl.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_pri_num.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_tree.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_undefs.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_reg_bank.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_shifter.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_undef_check.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_undefs.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_miim_wrapper.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_rx_buffer_to_ahb.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_rx_to_buffer.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_rx_wrapper.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_sdp_wrapper_32bit.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_top.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_tx_wrapper.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_wrapper.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_gpio.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_ahbif_ctrl.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_arbiter.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_async_fifo_clr.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_config.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_const.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_ctrl.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_eilmif_ctrl.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_fifo.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_gck.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_pad_lib.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_reg.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_regif.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_regif_ctrl.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_spiif.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_sync.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_sync_l2l.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_sync_p2p.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_to_iop.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_dualtimers.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_dualtimers_defs.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_dualtimers_frc.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_spi.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_timer.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_autocorrelation.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_balancefilter.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_collector.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_crngt_to_trng.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dx_inv_chain.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dx_trng_top.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_ff.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_interrupt_low.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_mux.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_mux_clk.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_sync.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_ehr.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_entropy_gen.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_gtech_models.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_lfsr_new.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_line.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_noise_gen.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_pmf_table.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_prng_top_wrap.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_reg_file.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_engine.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_misc.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_top.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_top_wrap_unconnected.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rosc.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rst_logic.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_sample_cntr.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_slave_bus_ifc.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_sync.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_tests_misc.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_top.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_uart.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_watchdog.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_watchdog_defs.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_watchdog_frc.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_iop_gpio.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\CortexM1.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\CortexM1Integration.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\CortexM1IntegrationWrapper.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ddr3_1_4code.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\DDR3_define.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ddr3_name.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ddr3_to_ahb_top.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\DDR3_TOP.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\dtcm.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\Gowin_EMPU_M1_top.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\GowinAhbExt.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\GowinCM1AhbExt.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\GowinCM1AhbExtWrapper.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_ahb_psram.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_apb_i2c.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_apb_int_wrapper.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_apb_sd.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_gpio.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\InputStage.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\itcm.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\MatrixDecodeS0.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\MatrixDecodeS1.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\MatrixDecodeS2.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputArb1.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputArb2.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputArb3.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputStage1.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputStage2.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputStage3.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\p_sse050_interconnect_f0_ahb_to_apb.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\p_sse050_interconnect_f0_apb_slave_mux.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\psram_code.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\psram_top.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\rng_addr_params.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\rng_cc_params.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\rng_params.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\Rtc.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcApbif.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcControl.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcCounter.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcInterrupt.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcParams.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcRevAnd.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcSynctoPCLK.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcUpdate.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\sse050_int_apb_decoder.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\sse050_integration_peripherals.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\sync_p2p.v<br>
E:\Gowin\Gowin_V1.9.9Beta-5\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\triple_speed_mac_name.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\gowin_empu_m1\temp\gw_empu_m1\cm1_option_defs.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\gowin_empu_m1\temp\gw_empu_m1\ahb_option_defs.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\gowin_empu_m1\temp\gw_empu_m1\can_parameter.vh<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_param.v<br>
C:\Users\sheiyi\Documents\Gowin_FPGA_Project\USB_AUDIO\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_define.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.9 Beta-5</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sat Oct 14 19:20:44 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>Gowin_EMPU_M1_Top</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 5s, Elapsed time = 0h 0m 7s, Peak memory usage = 80.070MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.077s, Peak memory usage = 80.070MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.386s, Peak memory usage = 80.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.101s, Peak memory usage = 80.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.345s, Peak memory usage = 80.070MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.068s, Peak memory usage = 80.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 80.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 80.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 80.070MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.364s, Peak memory usage = 80.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.083s, Peak memory usage = 80.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.126s, Peak memory usage = 80.070MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 15s, Elapsed time = 0h 0m 15s, Peak memory usage = 80.320MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.49s, Peak memory usage = 80.320MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.296s, Peak memory usage = 80.320MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 22s, Elapsed time = 0h 0m 24s, Peak memory usage = 80.320MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>53</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>53</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>19</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>34</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>1462</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFF</td>
<td>10</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFSE</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFR</td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFRE</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFP</td>
<td>22</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFPE</td>
<td>70</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFC</td>
<td>344</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>1011</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>3612</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>301</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>1049</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>2262</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>43</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>43</td>
</tr>
<tr>
<td class="label"><b>SSRAM </b></td>
<td>20</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspRAM16S4</td>
<td>4</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspRAM16SDP4</td>
<td>16</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>3</td>
</tr>
<tr>
<td class="label"><b>DSP </b></td>
<td></td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspMULT36X36</td>
<td>1</td>
</tr>
<tr>
<td class="label"><b>BSRAM </b></td>
<td>32</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSP</td>
<td>32</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>3778(3615 LUT, 43 ALU, 20 RAM16) / 20736</td>
<td>19%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>1462 / 16173</td>
<td>10%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>1462 / 16173</td>
<td>10%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>32 / 46</td>
<td>70%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>HCLK</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>HCLK_ibuf/I </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>HCLK</td>
<td>100.0(MHz)</td>
<td>106.4(MHz)</td>
<td>15</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.605</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.223</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>HCLK[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>HCLK[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>HCLK</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>HCLK_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>1515</td>
<td>HCLK_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>8</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]</td>
</tr>
<tr>
<td>1.849</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>7</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]</td>
</tr>
<tr>
<td>2.086</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0</td>
</tr>
<tr>
<td>2.602</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F</td>
</tr>
<tr>
<td>2.839</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1</td>
</tr>
<tr>
<td>3.395</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F</td>
</tr>
<tr>
<td>3.632</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1</td>
</tr>
<tr>
<td>4.187</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F</td>
</tr>
<tr>
<td>4.424</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1</td>
</tr>
<tr>
<td>4.994</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT</td>
</tr>
<tr>
<td>4.994</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN</td>
</tr>
<tr>
<td>5.029</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT</td>
</tr>
<tr>
<td>5.029</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN</td>
</tr>
<tr>
<td>5.064</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT</td>
</tr>
<tr>
<td>5.064</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN</td>
</tr>
<tr>
<td>5.099</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT</td>
</tr>
<tr>
<td>5.099</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN</td>
</tr>
<tr>
<td>5.134</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT</td>
</tr>
<tr>
<td>5.134</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN</td>
</tr>
<tr>
<td>5.170</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT</td>
</tr>
<tr>
<td>5.170</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN</td>
</tr>
<tr>
<td>5.205</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT</td>
</tr>
<tr>
<td>5.205</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN</td>
</tr>
<tr>
<td>5.240</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT</td>
</tr>
<tr>
<td>5.240</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN</td>
</tr>
<tr>
<td>5.275</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT</td>
</tr>
<tr>
<td>5.275</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN</td>
</tr>
<tr>
<td>5.310</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT</td>
</tr>
<tr>
<td>5.310</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN</td>
</tr>
<tr>
<td>5.346</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT</td>
</tr>
<tr>
<td>5.346</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN</td>
</tr>
<tr>
<td>5.381</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT</td>
</tr>
<tr>
<td>5.381</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN</td>
</tr>
<tr>
<td>5.416</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT</td>
</tr>
<tr>
<td>5.416</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN</td>
</tr>
<tr>
<td>5.451</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT</td>
</tr>
<tr>
<td>5.451</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN</td>
</tr>
<tr>
<td>5.486</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT</td>
</tr>
<tr>
<td>5.486</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN</td>
</tr>
<tr>
<td>5.522</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT</td>
</tr>
<tr>
<td>5.522</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN</td>
</tr>
<tr>
<td>5.557</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT</td>
</tr>
<tr>
<td>5.557</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN</td>
</tr>
<tr>
<td>5.592</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT</td>
</tr>
<tr>
<td>5.592</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN</td>
</tr>
<tr>
<td>5.627</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT</td>
</tr>
<tr>
<td>5.627</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN</td>
</tr>
<tr>
<td>5.662</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT</td>
</tr>
<tr>
<td>5.662</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN</td>
</tr>
<tr>
<td>5.698</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT</td>
</tr>
<tr>
<td>5.698</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN</td>
</tr>
<tr>
<td>5.733</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT</td>
</tr>
<tr>
<td>5.733</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN</td>
</tr>
<tr>
<td>5.768</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT</td>
</tr>
<tr>
<td>5.768</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN</td>
</tr>
<tr>
<td>5.803</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT</td>
</tr>
<tr>
<td>5.803</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN</td>
</tr>
<tr>
<td>5.838</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/COUT</td>
</tr>
<tr>
<td>5.838</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/CIN</td>
</tr>
<tr>
<td>5.874</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/COUT</td>
</tr>
<tr>
<td>5.874</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/CIN</td>
</tr>
<tr>
<td>5.909</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/COUT</td>
</tr>
<tr>
<td>5.909</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/CIN</td>
</tr>
<tr>
<td>5.944</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/COUT</td>
</tr>
<tr>
<td>5.944</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/CIN</td>
</tr>
<tr>
<td>6.414</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/SUM</td>
</tr>
<tr>
<td>6.651</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s8/I1</td>
</tr>
<tr>
<td>7.206</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s8/F</td>
</tr>
<tr>
<td>7.443</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s4/I2</td>
</tr>
<tr>
<td>7.896</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s4/F</td>
</tr>
<tr>
<td>8.133</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I2</td>
</tr>
<tr>
<td>8.586</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F</td>
</tr>
<tr>
<td>8.823</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s3/I1</td>
</tr>
<tr>
<td>9.378</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s3/F</td>
</tr>
<tr>
<td>9.615</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/I3</td>
</tr>
<tr>
<td>9.986</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/F</td>
</tr>
<tr>
<td>10.223</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>HCLK</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>HCLK_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>1515</td>
<td>HCLK_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 6.521, 69.670%; route: 2.607, 27.851%; tC2Q: 0.232, 2.479%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.707</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.121</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>HCLK[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>HCLK[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>HCLK</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>HCLK_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>1515</td>
<td>HCLK_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>8</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]</td>
</tr>
<tr>
<td>1.849</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>7</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]</td>
</tr>
<tr>
<td>2.086</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0</td>
</tr>
<tr>
<td>2.602</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F</td>
</tr>
<tr>
<td>2.839</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1</td>
</tr>
<tr>
<td>3.395</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F</td>
</tr>
<tr>
<td>3.632</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1</td>
</tr>
<tr>
<td>4.187</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F</td>
</tr>
<tr>
<td>4.424</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1</td>
</tr>
<tr>
<td>4.994</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT</td>
</tr>
<tr>
<td>4.994</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN</td>
</tr>
<tr>
<td>5.029</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT</td>
</tr>
<tr>
<td>5.029</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN</td>
</tr>
<tr>
<td>5.064</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT</td>
</tr>
<tr>
<td>5.064</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN</td>
</tr>
<tr>
<td>5.099</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT</td>
</tr>
<tr>
<td>5.099</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN</td>
</tr>
<tr>
<td>5.134</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT</td>
</tr>
<tr>
<td>5.134</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN</td>
</tr>
<tr>
<td>5.170</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT</td>
</tr>
<tr>
<td>5.170</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN</td>
</tr>
<tr>
<td>5.205</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT</td>
</tr>
<tr>
<td>5.205</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN</td>
</tr>
<tr>
<td>5.240</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT</td>
</tr>
<tr>
<td>5.240</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN</td>
</tr>
<tr>
<td>5.275</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT</td>
</tr>
<tr>
<td>5.275</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN</td>
</tr>
<tr>
<td>5.310</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT</td>
</tr>
<tr>
<td>5.310</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN</td>
</tr>
<tr>
<td>5.346</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT</td>
</tr>
<tr>
<td>5.346</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN</td>
</tr>
<tr>
<td>5.381</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT</td>
</tr>
<tr>
<td>5.381</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN</td>
</tr>
<tr>
<td>5.416</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT</td>
</tr>
<tr>
<td>5.416</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN</td>
</tr>
<tr>
<td>5.451</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT</td>
</tr>
<tr>
<td>5.451</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN</td>
</tr>
<tr>
<td>5.486</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT</td>
</tr>
<tr>
<td>5.486</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN</td>
</tr>
<tr>
<td>5.522</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT</td>
</tr>
<tr>
<td>5.522</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN</td>
</tr>
<tr>
<td>5.557</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT</td>
</tr>
<tr>
<td>5.557</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN</td>
</tr>
<tr>
<td>5.592</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT</td>
</tr>
<tr>
<td>5.592</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN</td>
</tr>
<tr>
<td>5.627</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT</td>
</tr>
<tr>
<td>5.627</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN</td>
</tr>
<tr>
<td>5.662</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT</td>
</tr>
<tr>
<td>5.662</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN</td>
</tr>
<tr>
<td>5.698</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT</td>
</tr>
<tr>
<td>5.698</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN</td>
</tr>
<tr>
<td>5.733</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT</td>
</tr>
<tr>
<td>5.733</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN</td>
</tr>
<tr>
<td>5.768</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT</td>
</tr>
<tr>
<td>5.768</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN</td>
</tr>
<tr>
<td>5.803</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT</td>
</tr>
<tr>
<td>5.803</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN</td>
</tr>
<tr>
<td>5.838</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/COUT</td>
</tr>
<tr>
<td>5.838</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/CIN</td>
</tr>
<tr>
<td>5.874</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/COUT</td>
</tr>
<tr>
<td>5.874</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/CIN</td>
</tr>
<tr>
<td>5.909</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/COUT</td>
</tr>
<tr>
<td>5.909</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/CIN</td>
</tr>
<tr>
<td>5.944</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/COUT</td>
</tr>
<tr>
<td>5.944</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/CIN</td>
</tr>
<tr>
<td>6.414</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/SUM</td>
</tr>
<tr>
<td>6.651</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s8/I1</td>
</tr>
<tr>
<td>7.206</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s8/F</td>
</tr>
<tr>
<td>7.443</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s4/I2</td>
</tr>
<tr>
<td>7.896</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s4/F</td>
</tr>
<tr>
<td>8.133</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I2</td>
</tr>
<tr>
<td>8.586</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F</td>
</tr>
<tr>
<td>8.823</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s3/I3</td>
</tr>
<tr>
<td>9.194</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s3/F</td>
</tr>
<tr>
<td>9.431</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s1/I2</td>
</tr>
<tr>
<td>9.884</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s1/F</td>
</tr>
<tr>
<td>10.121</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>HCLK</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>HCLK_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>1515</td>
<td>HCLK_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 6.419, 69.336%; route: 2.607, 28.158%; tC2Q: 0.232, 2.506%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.707</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.121</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>HCLK[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>HCLK[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>HCLK</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>HCLK_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>1515</td>
<td>HCLK_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>8</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]</td>
</tr>
<tr>
<td>1.849</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>7</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]</td>
</tr>
<tr>
<td>2.086</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0</td>
</tr>
<tr>
<td>2.602</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F</td>
</tr>
<tr>
<td>2.839</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1</td>
</tr>
<tr>
<td>3.395</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F</td>
</tr>
<tr>
<td>3.632</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1</td>
</tr>
<tr>
<td>4.187</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F</td>
</tr>
<tr>
<td>4.424</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1</td>
</tr>
<tr>
<td>4.994</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT</td>
</tr>
<tr>
<td>4.994</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN</td>
</tr>
<tr>
<td>5.029</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT</td>
</tr>
<tr>
<td>5.029</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN</td>
</tr>
<tr>
<td>5.064</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT</td>
</tr>
<tr>
<td>5.064</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN</td>
</tr>
<tr>
<td>5.099</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT</td>
</tr>
<tr>
<td>5.099</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN</td>
</tr>
<tr>
<td>5.134</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT</td>
</tr>
<tr>
<td>5.134</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN</td>
</tr>
<tr>
<td>5.170</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT</td>
</tr>
<tr>
<td>5.170</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN</td>
</tr>
<tr>
<td>5.205</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT</td>
</tr>
<tr>
<td>5.205</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN</td>
</tr>
<tr>
<td>5.240</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT</td>
</tr>
<tr>
<td>5.240</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN</td>
</tr>
<tr>
<td>5.275</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT</td>
</tr>
<tr>
<td>5.275</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN</td>
</tr>
<tr>
<td>5.310</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT</td>
</tr>
<tr>
<td>5.310</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN</td>
</tr>
<tr>
<td>5.346</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT</td>
</tr>
<tr>
<td>5.346</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN</td>
</tr>
<tr>
<td>5.381</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT</td>
</tr>
<tr>
<td>5.381</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN</td>
</tr>
<tr>
<td>5.416</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT</td>
</tr>
<tr>
<td>5.416</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN</td>
</tr>
<tr>
<td>5.451</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT</td>
</tr>
<tr>
<td>5.451</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN</td>
</tr>
<tr>
<td>5.486</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT</td>
</tr>
<tr>
<td>5.486</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN</td>
</tr>
<tr>
<td>5.522</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT</td>
</tr>
<tr>
<td>5.522</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN</td>
</tr>
<tr>
<td>5.557</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT</td>
</tr>
<tr>
<td>5.557</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN</td>
</tr>
<tr>
<td>5.592</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT</td>
</tr>
<tr>
<td>5.592</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN</td>
</tr>
<tr>
<td>5.627</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT</td>
</tr>
<tr>
<td>5.627</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN</td>
</tr>
<tr>
<td>5.662</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT</td>
</tr>
<tr>
<td>5.662</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN</td>
</tr>
<tr>
<td>5.698</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT</td>
</tr>
<tr>
<td>5.698</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN</td>
</tr>
<tr>
<td>5.733</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT</td>
</tr>
<tr>
<td>5.733</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN</td>
</tr>
<tr>
<td>5.768</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT</td>
</tr>
<tr>
<td>5.768</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN</td>
</tr>
<tr>
<td>5.803</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT</td>
</tr>
<tr>
<td>5.803</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN</td>
</tr>
<tr>
<td>5.838</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/COUT</td>
</tr>
<tr>
<td>5.838</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/CIN</td>
</tr>
<tr>
<td>5.874</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/COUT</td>
</tr>
<tr>
<td>5.874</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/CIN</td>
</tr>
<tr>
<td>5.909</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/COUT</td>
</tr>
<tr>
<td>5.909</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/CIN</td>
</tr>
<tr>
<td>5.944</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/COUT</td>
</tr>
<tr>
<td>5.944</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/CIN</td>
</tr>
<tr>
<td>6.414</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/SUM</td>
</tr>
<tr>
<td>6.651</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s8/I1</td>
</tr>
<tr>
<td>7.206</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s8/F</td>
</tr>
<tr>
<td>7.443</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s4/I2</td>
</tr>
<tr>
<td>7.896</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s4/F</td>
</tr>
<tr>
<td>8.133</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I2</td>
</tr>
<tr>
<td>8.586</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F</td>
</tr>
<tr>
<td>8.823</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s3/I3</td>
</tr>
<tr>
<td>9.194</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s3/F</td>
</tr>
<tr>
<td>9.431</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s1/I2</td>
</tr>
<tr>
<td>9.884</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s1/F</td>
</tr>
<tr>
<td>10.121</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>HCLK</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>HCLK_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>1515</td>
<td>HCLK_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>15</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 6.419, 69.336%; route: 2.607, 28.158%; tC2Q: 0.232, 2.506%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.717</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.111</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>HCLK[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>HCLK[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>HCLK</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>HCLK_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>1515</td>
<td>HCLK_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>8</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]</td>
</tr>
<tr>
<td>1.849</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>7</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]</td>
</tr>
<tr>
<td>2.086</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0</td>
</tr>
<tr>
<td>2.602</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F</td>
</tr>
<tr>
<td>2.839</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1</td>
</tr>
<tr>
<td>3.395</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F</td>
</tr>
<tr>
<td>3.632</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1</td>
</tr>
<tr>
<td>4.187</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F</td>
</tr>
<tr>
<td>4.424</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1</td>
</tr>
<tr>
<td>4.994</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT</td>
</tr>
<tr>
<td>4.994</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN</td>
</tr>
<tr>
<td>5.029</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT</td>
</tr>
<tr>
<td>5.029</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN</td>
</tr>
<tr>
<td>5.064</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT</td>
</tr>
<tr>
<td>5.064</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN</td>
</tr>
<tr>
<td>5.099</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT</td>
</tr>
<tr>
<td>5.099</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN</td>
</tr>
<tr>
<td>5.134</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT</td>
</tr>
<tr>
<td>5.134</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN</td>
</tr>
<tr>
<td>5.170</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT</td>
</tr>
<tr>
<td>5.170</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN</td>
</tr>
<tr>
<td>5.205</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT</td>
</tr>
<tr>
<td>5.205</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN</td>
</tr>
<tr>
<td>5.240</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT</td>
</tr>
<tr>
<td>5.240</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN</td>
</tr>
<tr>
<td>5.275</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT</td>
</tr>
<tr>
<td>5.275</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN</td>
</tr>
<tr>
<td>5.310</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT</td>
</tr>
<tr>
<td>5.310</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN</td>
</tr>
<tr>
<td>5.346</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT</td>
</tr>
<tr>
<td>5.346</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN</td>
</tr>
<tr>
<td>5.381</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT</td>
</tr>
<tr>
<td>5.381</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN</td>
</tr>
<tr>
<td>5.416</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT</td>
</tr>
<tr>
<td>5.416</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN</td>
</tr>
<tr>
<td>5.451</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT</td>
</tr>
<tr>
<td>5.451</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN</td>
</tr>
<tr>
<td>5.486</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT</td>
</tr>
<tr>
<td>5.486</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN</td>
</tr>
<tr>
<td>5.522</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT</td>
</tr>
<tr>
<td>5.522</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN</td>
</tr>
<tr>
<td>5.557</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT</td>
</tr>
<tr>
<td>5.557</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN</td>
</tr>
<tr>
<td>5.592</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT</td>
</tr>
<tr>
<td>5.592</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN</td>
</tr>
<tr>
<td>5.627</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT</td>
</tr>
<tr>
<td>5.627</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN</td>
</tr>
<tr>
<td>5.662</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT</td>
</tr>
<tr>
<td>5.662</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN</td>
</tr>
<tr>
<td>5.698</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT</td>
</tr>
<tr>
<td>5.698</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN</td>
</tr>
<tr>
<td>5.733</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT</td>
</tr>
<tr>
<td>5.733</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN</td>
</tr>
<tr>
<td>5.768</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT</td>
</tr>
<tr>
<td>5.768</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN</td>
</tr>
<tr>
<td>5.803</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT</td>
</tr>
<tr>
<td>5.803</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN</td>
</tr>
<tr>
<td>5.838</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/COUT</td>
</tr>
<tr>
<td>5.838</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/CIN</td>
</tr>
<tr>
<td>5.874</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/COUT</td>
</tr>
<tr>
<td>5.874</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/CIN</td>
</tr>
<tr>
<td>5.909</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/COUT</td>
</tr>
<tr>
<td>5.909</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/CIN</td>
</tr>
<tr>
<td>5.944</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/COUT</td>
</tr>
<tr>
<td>5.944</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/CIN</td>
</tr>
<tr>
<td>6.414</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/SUM</td>
</tr>
<tr>
<td>6.651</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s8/I1</td>
</tr>
<tr>
<td>7.206</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s8/F</td>
</tr>
<tr>
<td>7.443</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s4/I2</td>
</tr>
<tr>
<td>7.896</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s4/F</td>
</tr>
<tr>
<td>8.133</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I2</td>
</tr>
<tr>
<td>8.586</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F</td>
</tr>
<tr>
<td>8.823</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s8/I3</td>
</tr>
<tr>
<td>9.194</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s8/F</td>
</tr>
<tr>
<td>9.431</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s6/I0</td>
</tr>
<tr>
<td>9.534</td>
<td>0.103</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s6/O</td>
</tr>
<tr>
<td>9.771</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s3/I0</td>
</tr>
<tr>
<td>9.874</td>
<td>0.103</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s3/O</td>
</tr>
<tr>
<td>10.111</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>HCLK</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>HCLK_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>1515</td>
<td>HCLK_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>14</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 6.172, 66.740%; route: 2.844, 30.751%; tC2Q: 0.232, 2.509%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.595</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.232</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/pc_31_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>HCLK[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>HCLK[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>HCLK</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>HCLK_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>1515</td>
<td>HCLK_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>8</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>4</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]</td>
</tr>
<tr>
<td>1.849</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>7</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]</td>
</tr>
<tr>
<td>2.086</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0</td>
</tr>
<tr>
<td>2.602</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F</td>
</tr>
<tr>
<td>2.839</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1</td>
</tr>
<tr>
<td>3.395</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F</td>
</tr>
<tr>
<td>3.632</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1</td>
</tr>
<tr>
<td>4.187</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F</td>
</tr>
<tr>
<td>4.424</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1</td>
</tr>
<tr>
<td>4.994</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT</td>
</tr>
<tr>
<td>4.994</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN</td>
</tr>
<tr>
<td>5.029</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT</td>
</tr>
<tr>
<td>5.029</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN</td>
</tr>
<tr>
<td>5.064</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT</td>
</tr>
<tr>
<td>5.064</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN</td>
</tr>
<tr>
<td>5.099</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT</td>
</tr>
<tr>
<td>5.099</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN</td>
</tr>
<tr>
<td>5.134</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT</td>
</tr>
<tr>
<td>5.134</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN</td>
</tr>
<tr>
<td>5.170</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT</td>
</tr>
<tr>
<td>5.170</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN</td>
</tr>
<tr>
<td>5.205</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT</td>
</tr>
<tr>
<td>5.205</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN</td>
</tr>
<tr>
<td>5.240</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT</td>
</tr>
<tr>
<td>5.240</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN</td>
</tr>
<tr>
<td>5.275</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT</td>
</tr>
<tr>
<td>5.275</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN</td>
</tr>
<tr>
<td>5.310</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT</td>
</tr>
<tr>
<td>5.310</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN</td>
</tr>
<tr>
<td>5.346</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT</td>
</tr>
<tr>
<td>5.346</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN</td>
</tr>
<tr>
<td>5.381</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT</td>
</tr>
<tr>
<td>5.381</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN</td>
</tr>
<tr>
<td>5.416</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT</td>
</tr>
<tr>
<td>5.416</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN</td>
</tr>
<tr>
<td>5.451</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT</td>
</tr>
<tr>
<td>5.451</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN</td>
</tr>
<tr>
<td>5.486</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT</td>
</tr>
<tr>
<td>5.486</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN</td>
</tr>
<tr>
<td>5.522</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT</td>
</tr>
<tr>
<td>5.522</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN</td>
</tr>
<tr>
<td>5.557</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT</td>
</tr>
<tr>
<td>5.557</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN</td>
</tr>
<tr>
<td>5.592</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT</td>
</tr>
<tr>
<td>5.592</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN</td>
</tr>
<tr>
<td>5.627</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT</td>
</tr>
<tr>
<td>5.627</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN</td>
</tr>
<tr>
<td>5.662</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT</td>
</tr>
<tr>
<td>5.662</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN</td>
</tr>
<tr>
<td>5.698</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT</td>
</tr>
<tr>
<td>5.698</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN</td>
</tr>
<tr>
<td>5.733</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT</td>
</tr>
<tr>
<td>5.733</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN</td>
</tr>
<tr>
<td>5.768</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT</td>
</tr>
<tr>
<td>5.768</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN</td>
</tr>
<tr>
<td>5.803</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT</td>
</tr>
<tr>
<td>5.803</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN</td>
</tr>
<tr>
<td>5.838</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/COUT</td>
</tr>
<tr>
<td>5.838</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/CIN</td>
</tr>
<tr>
<td>5.874</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/COUT</td>
</tr>
<tr>
<td>5.874</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/CIN</td>
</tr>
<tr>
<td>5.909</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/COUT</td>
</tr>
<tr>
<td>5.909</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/CIN</td>
</tr>
<tr>
<td>5.944</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/COUT</td>
</tr>
<tr>
<td>5.944</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/CIN</td>
</tr>
<tr>
<td>5.979</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/COUT</td>
</tr>
<tr>
<td>5.979</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_31_s/CIN</td>
</tr>
<tr>
<td>6.449</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>6</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_31_s/SUM</td>
</tr>
<tr>
<td>6.686</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/biu_addr_31_s/I1</td>
</tr>
<tr>
<td>7.241</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/biu_addr_31_s/F</td>
</tr>
<tr>
<td>7.478</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/pre_fetch_addr_31_s0/I0</td>
</tr>
<tr>
<td>7.995</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/pre_fetch_addr_31_s0/F</td>
</tr>
<tr>
<td>8.232</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/pc_31_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>HCLK</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>HCLK_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>1515</td>
<td>HCLK_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/pc_31_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/pc_31_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>12</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 5.242, 71.125%; route: 1.896, 25.727%; tC2Q: 0.232, 3.148%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
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